A Low Power Area Efficient Design for 1-bit Full Adder Cell
نویسنده
چکیده
In this paper we present a 1 bit Full Adder Cell. It was implemented with lesser number of transistors and lesser power consumption compared to the existing implementations of the Full Adder. Simulations are carried for supply voltages of 1.2v, 0.8v in HSPICE at 0.18μmCMOS technology. Proposed Full Adder results show that there was a reduction of power consumption and efficient in area. Area was measured using Micro Wind Tool. Keywords— Majority Function, Area , Power Consumption.
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